Japanese scientists make mini memory chips with 3D data storage
New 3D stacked memory cells may revolutionize the concept of memory chips
By Kiran N. Kumar
From huge memory diskettes to compact discs to flash drives, the sizes of computer media formats and memory devices have steadily decreased.
Japanese scientists, who had pioneered the miniaturization of floppy disks into CDs, have once again taken an important step by developing a new 3D stacked memory cell that can revolutionize the concept of memory chips.
While new machine learning, artificial intelligence (AI) and big data are the new buzzwords in the tech world, cloud-enabled mobile devices require greater memory, power efficiency and smaller size.
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Currently, flash memory devices require relatively large currents to read or write data which will change with newer 3D memory devices.
Making strides in the direction, a team of researchers from the University of Tokyo’s Institute of Industrial Sciences fabricated three-dimensional vertically formed field-effect transistors to produce high-density data storage devices.
This proof-of-concept 3D stacked memory cell is based on ferroelectric and antiferroelectric field-effect transistors (FETs) with oxide semiconductor channels deposited on an atomic layer.
These FETs can store ones and zeros non-volatile, without the need for constant power. This means that the vertical structure of the device increases information density and reduces operating power requirements.
By depositing layers of hafnium oxide and indium oxide in a vertical trench structure, they fabricated ferroelectric materials with electric dipoles that are most stable when aligned in the same direction.
Moreover, the ferroelectric hafnium oxide spontaneously allows the vertical alignment of the dipoles. Information is stored by the degree of polarization in the ferroelectric layer, which can be read by the system due to changes in electrical resistance.
On the other hand, antiferroelectrics like to alternate up and down dipoles in the erased state, enabling efficient erasing operations in the oxide semiconductor channel, the scientists said.
To be precise, by using an antiferroelectric instead of a ferroelectric, they found that only a tiny net charge was needed to erase the data, leading to more efficient write operations. Therefore, the way forward allows for new, even smaller and more environmentally friendly data storage devices.
“We showed that our device was stable for at least 1,000 cycles,” said lead author Zhuo Li. The team experimented with different thicknesses for the indium oxide layer and found that optimizing this setting can cause significant performance increases.
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The researchers also used first principles computer simulations to plot the most stable surface states.
“Our approach has the potential to significantly improve the field of nonvolatile memory,” says lead author Masaharu Kobayashi. This type of research using both experimental prototypes coupled with computer simulations can help enable the consumer electronics of the future.
The work was published in 2022 IEEE Silicon Nanoelectronics Workshop on High-Density Memory.