Field effect transistors for high density data storage devices
The University of Tokyo’s Institute of Industrial Sciences used a ferroelectric gate insulator and an oxide semiconductor channel deposited on an atomic layer to build vertically-structured three-dimensional field-effect transistors for storage devices high density data.
Additionally, the researchers found that by using an antiferroelectric rather than a ferroelectric, they were able to erase data with only a small net charge, resulting in more efficient write operations. This research could lead to new, even smaller and more environmentally friendly data storage memory.
In terms of data storage, consumer flash drives already surpass earlier computer media formats in size, capacity and affordability, but new machine learning and big data applications continue to fuel the need. of advancement.
Additionally, future Internet of Things nodes and cloud-enabled mobile devices will require memory that is both energy efficient and compact. However, modern flash memory technologies require fairly large currents to read or write information.
The University of Tokyo has now produced a proof-of-concept 3D stacked memory cell based on ferroelectric and antiferroelectric field-effect transistors (FETs) with an oxide semiconductor channel deposited on an atomic layer. These FETs can hold ones and zeros in a non-volatile fashion, meaning they don’t need constant power.
The device’s vertical structure increases data density while reducing operating power requirements. In a vertical trench structure, layers of hafnium oxide and indium oxide have formed. Electric dipoles in ferroelectric materials are strongest when facing the same direction. The vertical alignment of the dipoles is naturally permitted by the ferroelectric hafnium oxide.
The degree of polarization in the ferroelectric layer stores data, which can be read by the system due to changes in electrical resistance. In the wiped state, antiferroelectrics, on the other side, prefer to move the dipoles up and down, enabling efficient erasing processes in the oxide semiconductor channel.
We have shown our device to be stable for at least 1,000 cycles.
Zhuo Li, first author of the study, University of Tokyo
The researchers experimented with different thicknesses of the indium oxide layer. They found that changing this setting can lead to significant performance gains. The scientists also plotted the most persistent surface states using first-principles computer simulations.
Our approach has the potential to significantly improve the field of non-volatile memory.
Masaharu Kobayashi, lead author of the study, University of Tokyo
This type of research, which combines experimental prototypes with computer models, could pave the way for future consumer devices.
The work is available in the IEEE Silicon Nanoelectronics Workshop 2022 as “Vertical Channel Ferroelectric/Anti-Ferroelectric FET with ALD InOx and Field-Induced Polar Axis Alignment for High Density 3D Memory”.
JST’s Intellectual Property Utilization Support Program, Super-Highway, Japan, funded this project.